1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a technique of forming a trench MOS gate which is applied to a power device.
2. Description of the Background Art
FIGS. 41 to 48 are sectional views showing a conventional process of forming trench MOS gates in step order. First, the structure shown in FIG. 41 is prepared. Referring to FIG. 41, the structure is obtained by successively stacking a P-type semiconductor layer 103 having a high impurity concentration, an N-type semiconductor layer 102 having a high impurity concentration, an N-type semiconductor layer 101 having a low impurity concentration and a P-type base layer 104 from the lower side, and trenches 200 are formed between an upper surface of the P-type base layer 104 and an intermediate portion of the N-type semiconductor layer 101. On the upper surface of the P-type base layer 104, N-type semiconductor layers 105 having a high impurity concentration are selectively formed around the trenches 200.
Then, a gate oxide film 111 is formed over the entire surface, including inner walls of the trenches 200, exposed on the upper side of the structure shown in FIG. 41 (FIG. 42). Further, a gate electrode material layer 112 of polysilicon or the like is provided on the gate oxide film 111, to fill up the trenches 200 (FIG. 43). Only the parts of the gate electrode material layer 112 filling up the trenches 200 are left as gate electrodes 113, and the remaining parts are removed by etching (FIG. 44).
Thereafter surfaces of the gate electrodes 113 are oxidized to form oxide films 115 (FIG. 45). P-type semiconductor layers 118 having a high impurity concentration are formed on parts of the P-type base layer 104 exposed between the adjacent N-type semiconductor layers 105 by ion implantation through the oxide films 111 or the like, and interlayer isolation films 116 and 117 are deposited in this order with oxide films formed by CVD, for example (FIG. 46). The interlayer isolation films 116 and 117 are selectively etched to be left only on the gate electrodes 113, as shown in FIG. 47.
Further, silicide layers 119 are formed on upper surfaces of the N-type semiconductor layers 105, the P-type semiconductor layers 118 and the gate electrodes 113 by sputtering or lamp annealing, and a barrier metal layer 120 and an aluminum interconnect line 121 are deposited on the overall surface (FIG. 48). FIG. 49 is a sectional view taken along the line Q-Q in FIG. 48. Referring to FIG. 49, isolation oxide films 122 and P-type semiconductor layers 123 are provided on both sides of each trench 200. The aluminum interconnect line 121 is connected with each gate electrode 113 on end portions of each trench 200 through the silicide layers 119 and the barrier metal layer 120.
The conventional trench MOS gates are formed in the aforementioned manner in the structure shown in FIGS. 48 and 49. Therefore, the gate oxide film 111 is locally reduced in thickness on openings C and bottom portions D of the trenches 200. Particularly in the openings C, convex corners appear in the gate oxide film 111 on the interfaces between the same and the gate electrodes 113. In the openings C, further, the gate oxide film 111 is damaged by etching of the gate electrode material layer 112 in the steps shown in FIGS. 43 and 44 to deteriorate the characteristics of the gate oxide film 111, as a first problem.
If the aluminum interconnect line 121 is inferior in flatness, the trench MOS gates are readily broken by an impact in an operation (on-cell bonding) of bonding aluminum thin wires of 50 to 400 μm in diameter to the aluminum interconnect line 121 in an assembly step for transistors employing the trench MOS gates. Further, contact areas of the aluminum interconnect line 121 and the aluminum thin wires may tend to be reduced, to increase the resistance in the contact parts. In this case, the resistance of the transistors employing the trench MOS gates is apparently increased in ON states, as a second problem.
If the aluminum interconnect line 121 is formed in a large thickness in order to solve the second problem, a wafer provided with the trench MOS gates so remarkably warps that it is difficult to carry out an exposure step, as a third problem.